Openlane is awesome, can convert RTL verilog to GDS
Verified die patterns exist for the 6502 and 4004, could implement something new if we wanted to
Keysight ADS also exists for amplifier design
Optical rectenna?
could make the world’s dumbest motor controller with a bunch of mems switches on a single package

Notes from research:

OpenCores is an organization with forums that are dead, they appear to have some RISC designs but they’ve made an interconnect standard called WISHBONE that seems to be less painful than AXI. Here’s the spec: https://cdn.opencores.org/downloads/wbspec_b4.pdf
There’s these things called Euler paths that make routing a bit easier. https://en.wikipedia.org/wiki/Eulerian_path
Historically we started with PMOS processes, then went to NMOS, then CMOS (which eliminates the pullup resistor and is therefore more power effecient)
Matt Venn is a god. He teaches a course called Zero to ASIC, which is $650 at the base tier. He brings student’s designs from Verilog, helps people harden their designs, and then puts them all on the same order and get them fabbed as ASICs. This uses the following process
- RTL design, in Verilog
- Simulation, in some suite that’s not necessarily

Matt Venn Hackaday talk:

Introduction to VLSI systems 1978 - dated in process, not too far off in terms of pedagogy
PDK - Process Design Kit - Library of all the specifications of a process used to fab chips
- Includes standard cells - what a transistor/inverter would look like at each scale
- Very large dataset, nearly 3.5GB for SKY130
- Have variants for low power/high density/etc
Library (LIB) - Standard cells electrical models
Library Exchange Format (LEF) - Abstract Layout of cells and finished designs
Design Exchange Format (DEF) - Design abstract layout
Standard Parasitic Exchange Format (SPEF) - RC values of design wires
Graphic Design System (GDS) - Final layout geometry